Metal-Free CVD Graphene Synthesis on 200 mm Ge/Si(001) Substrates.

Abstract

Good quality, complementary-metal-oxide-semiconductor (CMOS) technology compatible, 200 mm graphene was obtained on Ge(001)/Si(001) wafers in this work. Chemical vapor depositions were carried out at the deposition temperatures of 885 °C using CH4 as carbon source on epitaxial Ge(100) layers, which were grown on Si(100), prior to the graphene synthesis. Graphene layer with the 2D/G ratio ∼3 and low D mode (i.e., low concentration of defects) was measured over the entire 200 mm wafer by Raman spectroscopy. A typical full-width-at-half-maximum value of 39 cm-1 was extracted for the 2D mode, further indicating that graphene of good structural quality was produced. The study also revealed that the lack of interfacial oxide correlates with superior properties of graphene. In order to evaluate electrical properties of graphene, its 2 × 2 cm2 pieces were transferred onto SiO2/Si substrates from Ge/Si wafers. The extracted sheet resistance and mobility values of transferred graphene layers were ∼1500 ± 100 Ω/sq and μ ≈ 400 ± 20 cm2/V s, respectively. The transferred graphene was free of metallic contaminations or mechanical damage. On the basis of results of DFT calculations, we attribute the high structural quality of graphene grown by CVD on Ge to hydrogen-induced reduction of nucleation probability, explain the appearance of graphene-induced facets on Ge(001) as a kinetic effect caused by surface step pinning at linear graphene nuclei, and clarify the orientation of graphene domains on Ge(001) as resulting from good lattice matching between Ge(001) and graphene nucleated on such nuclei.