MEPHISTO – a 128-channel front end chip with real time data sparsification and multi-hit capability

Abstract

The MEPHISTO chip uses a novel binary architecture to achieve a high speed readout for multichannel detectors, like silicon strip detectors or MSGCs. The architecture is an alternative to existing designs with raw data pipelines as are commonly used in particle physics applications. The chip receives 128 digital input signals from an analog front end chip at a rate of up to 80 MHz. The hit pattern is sparsified in real time and only the addresses and interaction times of hits are stored temporarily in FIFOs. Multiple hits per event are possible. A trigger selects interesting events for readout. All other hits are automatically discarded. Untriggered readout at high rates is also possible. The occupied chip area depends on the average data rate which can be very small in many applications. Very compact designs with up to ten times less first level storage can therefore be realized.