Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies

The characteristic pinched hysteresis behavior of memristors has been reported by stacks of a variety of materials. This paper aims to examine the principles of logic design using such two terminal memristive systems for high performance digital circuit applications. As against logic design with standard CMOS, the benefits of logic design with memristors have been stated. The realization and operation of memristor based AND and OR hybrid logic gates obtained by integrating memristors with standard CMOS logic have been discussed. The IMPLY and MAGIC logic families have been demonstrated by covering MAGIC NOR and NAND logic gate implementation with MAGIC NOR in detail. A qualitative comparison has been drawn towards the end of the paper to conclude on the suitability and application space for each of the logic families studied in this paper. This work also describes the hybrid CMOS-memristive logic family known as MRL (Memristor Ratioed Logic). With the addition of CMOS inverters, this logic family's OR and AND logic gates, which are based on memristive components, are given a full logic structure and signal restoration. The MRL family, in contrast to earlier memristor-based logic families, is compatible with conventional CMOS logic.

Active loaded source-coupled logic: Applications and performance comparison

The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this device technology, with several emerging applications including that of logic circuits. Several memristive logic families have been proposed, each with different attributes, in the current quest for energy-efficient computing systems of the future. However, limited endurance of memristor devices and variations (both cycle-to-cycle and device-to-device) are important parameters to be considered in the evaluation of such logic families. In this work we build upon an accurate physics-based model of a bipolar metal-oxide resistive RAM device (supporting parasitics of the device structure and variability of switching voltages and resistance states) and use it to show how performance of memristor-based logic circuits can de degraded owing to both variability and state-drift impact. Based on previous work on CMOS-like memristive logic circuits, we propose a memristive ratioed logic scheme, which is crossbar-compatible, i.e. suitable for in-/near-memory computing, and tolerant to device variability, while also it does not affect the device endurance since computations do not involve switching the memristor states. As a figure of merit, we compare such new logic scheme with MAGIC, focusing on the universal NOR logic gate.

Dynamic differential signaling based logic families for robust ultra-low power near-threshold computing

Amongst several emergent applications of the memristance switching phenomenon, the implementation of logic circuits is gaining considerable attention. Memristor-based logic circuits open new pathways for the exploration of advanced computing architectures as promising alternatives to conventional integrated circuit technologies. However, up to now no standard logic design methodology exists, since it is not immediately clear what kind of computing architectures would in practice benefit the most from the computing capabilities of memristors. This chapter addresses memristive logic circuit design and computational methodologies, aiming to approach this novel area of research while motivating for further research on innovative design strategies, which comply with emerging technologies. First, a summary of the most recognized memristive logic circuit design concepts is provided. Then two novel logic design paradigms are presented, which aim to address several drawbacks of other existing design concepts in the literature, and to facilitate the incorporation of memristors in currently established logic circuit architectures. Thus they could be promising candidates to be used in future electronic systems design. The proposed design paradigms are validated through SPICE-based simulations for a variety of complex combinational logic circuits.

Conventional complementary metal-oxide-semiconductor (CMOS) technology is now approaching its physical scaling limits to enable Moore’s law to continue. Spintronic devices, as one of the potential alternatives, show great promise to replace CMOS technology for next-generation low-power integrated circuits in nanoscale technology nodes. Until now, spintronic memory has been successfully commercialized. However spintronic logic still faces many critical challenges (e.g. direct cascading capability and small operation gain) before it can be practically applied. In this paper, we propose a standard complimentary spintronic logic (CSL) design methodology to form a CMOS-like logic design paradigm. Using the spin Hall effect (SHE)-driven magnetic tunnel junction (MTJ) device as an example, we demonstrate CSL implementation, functionality and performance. This logic family provides a unified design methodology for spintronic logic circuits and partly solves the challenges of direct cascading capability and small operation gain in the previously proposed spintronic logic designs. By solving a modified Landau–Lifshitz–Gilbert equation, the magnetization dynamics in the free layer of the MTJ is theoretically described and a compact electrical model is developed. With this electrical model, numerical simulations have been performed to evaluate the functionality and performance of the proposed CSL design. Simulation results demonstrate that the proposed CSL design paradigm is rather promising for low-power logic computing.

Multiple valued logic (MVL) circuits are particularly attractive for nanoscale implementation as advantages in information density and operating speed can be harvested using emerging technologies. In this paper, a new family of MVL gates is proposed for implementation using carbon nanotube field-effect transistors (CNTFETs). The proposed designs use pseudo N-type CNTFETs and no resistor is utilized for their operation. This approach exploits threshold voltage control of the P-type and N-type transistors, while ensuring correct MVL operation for both ternary and quaternary logic gates. This paper provides a detailed assessment of several figures of merit, such as static power consumption, switching power consumption, propagation delay and the power-delay product (PDP). Compared with resistor-loaded designs, the proposed pseudo-NCNTFET MVL gates show advantages in circuit area, power consumption and energy efficiency, while still incurring a comparable propagation delay. Compared to a complementary logic family, the pseudo-NCNTFET MVL logic family requires a smaller circuit area with a similar propagation delay on average, albeit with a larger PDP and static power consumption. A design methodology and a discussion of issues related to leakage and yield are also provided for the proposed MVL logic family.

‘Memristor’ is a new emerging nanodevice that is gaining a lot of appreciation from the researchers these days. They possess dual properties of resistor, memory and find immense application in the fields of nanoelectronic circuit and memory designs. Material implication logic is applied in memristor-based circuit designs as it can be performed easily using two memristors and one resistor. In this paper a memristor-based T (toggle) flip-flop is implemented using material implication logic. Thereby this T flip-flop is employed in designing an Up-Down counter, based on the implication operations using memristors. The designs thus presented for the T flip-flop and counter need 6, 16 memristors respectively. Memristor technology being highly dense, our counter design will occupy lesser area as compared to its conventional CMOS-based design. Also the proposed T flip flop takes 11 computation steps to generate its outputs and 52 steps are needed by the Up-Down counter to perform its operation. Moreover in our memristor-based counter circuit, counting can be started, stopped and resumed at any desired logic states by simply controlling the externally applied voltages.

1. Review of Linear Circuit Theory. Kirchhoff's voltage and current laws. Voltage bus notation. Definition of voltage-current characteristic. Superposition in linear circuits. Resistive circuits. Thevenin equivalent circuits. Norton equivalent circuits. Voltage and current division. Single time constant resistor-capacitor circuits. 2. Operational Amplifiers. Integrated-circuit operational amplifier. Simplified Op-amp model. Simplified Op-amp model. Ideal Op-amp approximation. Linear op-amp circuits. Nonlinear operational amplifier circuits. Nonideal properties of operational amplifiers. 3. Introduction to Nonlinear Circuit Elements. Basic properties of nonlinear elements. Graphical analysis with one nonlinear circuit element. Examples of two-terminal nonlinear devices. Graphical method with time-varying sources. Iterative mathematical solutions. Piecewise linear modeling of two-terminal nonlinear devices. 4. Signal Processing and Conditioning with Two-terminal Nonlinear Devices. The transfer characteristic. Clipping and limiting circuits. Rectifier circuits. Power supply circuits. Precision rectifier circuits. 5. Three Terminal Devices. Definition of a three terminal device. Field-effect transistors. Bipolar-junction transistor. Upward slope of transistor V-1 characteristics. Photonic devices. Temperature dependence of devices. Power limitations of device operation. 6. Basic Circuits Containing Three-Terminal Devices. Inverter configuration. Voltage-follower configuration. Current-follower configuration. Operation in the digital regime. 7. Analog Amplification. Definition of a signal. Active and passive circuits. Biasing. Small-signal modeling of analog circuits. Two-port amplifier representation. 8. Differential Amplifiers. Basic differential-amplifier topology. Differential- and common-mode signals. BJT differential amplifier. MOSFET and JFET differential amplifiers. Large-signal performance of differential amplifiers. 9. Frequency Response and Time-Dependent Circuit Behavior. Sources of capacitance and inductance in electronic circuits. Sinusoidal steady-state amplifier response. Frequency response of circuits containing capacitors. Frequency response of the differential amplifier. Time response of electronic circuits. 10. Feedback and Stability. The negative-feedback loop. General requirements of feedback circuits. Effects of feedback on amplifier performance. The four basic amplifier types. The four feedback topologies. Effect of feedback connections on amplifier port resistance. Examples of real feedback amplifiers. Feedback-loop stability. 11. Multistage and Power Amplifiers. Input and output loading. Two-port amplifier cascade. Multistage amplifier biasing. DC level shifting. Differential-amplifier cascade. Power-amplification output stages. Integrated-circuit power amplifiers. Power devices. 12. Analog Integrated Circuits. Basic operational-amplifier cascade. Case Study: The LM741 Bipolar operational amplifier. Case Study: A simple CMOS Operational Amplifier. 13. Active Filters and Oscillators. A simple first-order active filter. Ideal filter functions. Second-order filter responses. Active filter cascading. Magnitude and frequency scaling. Switched-capacitor networks and filters. Oscillators. 14. Digital Circuits. Fundamental concepts of digital circuits. CMOS logic family. NMOS logic family. TTL logic family. Emitter-coupled logic family. BiCMOS logic circuits. 15. Fundamentals of Digital Systems. Sequential logic circuits. Multivibrator circuits. Digital memory. Analog-to-digital interfacing. 16. Electronic Design. An overview of the design process. The tools of electronic design. Open-ended design problems. Analog integrated-circuit design problems. Appendix A: Physics of Semiconductor Devices. Electronic materials. Qualitative description of holes. Impurities. Carrier densities within a semiconductor. Current flow in a semiconductor. Diffusion gradient within a semiconductor. Derivation of the v-i characteristic of the PN junction diode. The bipolar junction transistor. The metal-oxide-semiconductor field-effect transistor. Appendix B: Semiconductor Device and Integrated Circuit Fabrication. An overview of the fabrication process. Epitaxial growth. Oxidation. Wafer doping. Film deposition. Wafer etching. Lithographic processing. A MOS fabrication sequence. A BJT fabrication sequence. Appendix C: Computer-Aided Circuit Design Using SPICE and PSpice. Use of SPICE. Capabilities of SPICE and PSPICE. Circuit description. Types of analyses. Generating output. References. Appendix D: Resistor Color Codes and Standard Values. Appendix E: Suggestions for Further Reading. Appendix F: Answers to Selected Problems.

In comparison to the conventional complementary pull-up and pull-down logic structure, the pass transistor logic (PTL) family reduces the number of transistors required to perform logic functions, thereby reducing both area and power consumption. However, this logic family requires inter-stage inverters to ensure signal integrity in cascaded logic circuits, and inverters must be used to provide each logical input signal in its complementary form. These inverters and complementary signals increase the device count and significantly degrade overall system efficiency. Dual-gate ambipolar field-effect transistors natively provide a single-transistor XNOR operation and permit highly-efficient and compact circuits due to their ambipolar capabilities. Similar to PTL, logic circuits based on ambipolar field-effect transistors require complementary signals. Therefore, numerous inverters are required, with significant energy and area costs. Ambipolar field-effect transistors are a natural match for PTL, as hybrid ambipolar-PTL circuits can simultaneously use these inverters to satisfy their necessity in both PTL and ambipolar circuits. We therefore propose a new hybrid ambipolar-PTL logic family that exploits the compact logic of PTL and the ambipolar capabilities of ambipolar field-effect transistors. Novel hybrid ambipolar-PTL circuits were designed and simulated in SPICE, demonstrating strong signal integrity along with the efficiency advantages of using the required inverters to simultaneously satisfy the requirements of PTL and ambipolar circuits. In comparison to the ambipolar field-effect transistors in the conventional CMOS logic structure, our hybrid full adder circuit can reduce propagation delay by 47%, energy consumption by 88%, energy-delay product by a factor of 9, and area-energy-delay product by a factor of 20.

Memristor-based combinational circuits: A design methodology for encoders/decoders

The VLSI design flow and methodologies provide a structured framework for transforming system-level specifications into a manufacturable integrated circuit. This chapter presents a detailed overview of the complete VLSI design flow, starting from requirement analysis and architectural design to logic design, circuit implementation, physical design, and final verification. Emphasis is placed on design abstraction levels, including behavioral, register-transfer level (RTL), gate-level, and layout-level representations, which enable efficient handling of increasing design complexity. The chapter also discusses commonly used design methodologies such as top-down and bottom-up approaches, along with modular and hierarchical design strategies. Key aspects of design verification, timing analysis, power optimization, and design-for-testability are highlighted to ensure functionality, performance, and reliability. By explaining both conventional and modern design methodologies, this chapter equips readers with a clear understanding of how complex VLSI systems are systematically developed, verified, and optimized for real-world applications.

We report experimental demonstration of Material Implication (IMP) logic using ZnO nanowire-based memristors. The logic is demonstrated with a high-to-low resistance ratio of only five. This imposes much less stringent requirements on memristor performance that can enable IMP logic operation with lower bit error rates. Process independence on memristor and memristor-based IMP logic performance is demonstrated, and a more practical implementation of logic is made by relaxing the restriction imposed on the ranges of the values of on and off state resistances. IMP logic is validated up to a clock frequency of 100 KHz.

This paper presents a new energy harvesting (EH) concept design, referred to as EH skin structure. A generic design and experimental verification methodology will be proposed to demonstrate the feasibility of the EH skin for practical applications. In the past, EH researches have primarily focused on designing a device-level energy harvester, such as a cantilever-type EH device. However, such a device-level energy harvester has several drawbacks: (i) need of an extra space for proof masses and fixture, (ii) significant energy loss due to the fixture, and (iii) need of a casing for EH device protection against environmental harms. While this new EH concept design could overcome the drawbacks above, there is no design methodology for EH skin. This paper proposes design and experimental verification methodology for EH skin structure. The design methodology comprises three tasks: (i) construction of a valid computational model, (ii) design optimization of EH skin, and (iii) experimental verification. An outdoor condensing unit of which a fan produces harmonic vibration is chosen for a case study because similar configuration of vibration can be found in many engineered systems (e.g., airplane wing, AC unit). The proposed design methodology determined an optimal EH skin configuration (sizes, locations, etc.) on the vibrating structure. The EH skin was carefully prototyped to demonstrate that it can generate power up to 3.7mW, which is sustainable for operating wireless sensor units for structural health monitoring or building automation.

Recently memristor-based applications and circuits are receiving an increased attention. Furthermore, memristors are also applied in logic circuit design. Material implication logic is one of the main areas with memristors. In this paper an optimized memristor-based full adder design by material implication logic is presented. This design needs 27 memristors and less area in comparison with typical CMOS-based 8-bit full adders. Also the presented full adder needs only 184 computational steps which enhance former full adder design speed by 20 percent.