Memristor-Based CMOS Hybrid Circuit Design and Analysis

Abstract

Electronic memory with ever-increasing storage capacity is always in high demand. Every year, a computer transforms into a smaller, faster, and more reliable device. Memristor is a passive aspect recently developed that is gaining popularity. The non-volatile and small area features of this element are very essential. A Memristor's ability to fabricate around CMOS architectures is a step forward in VLSI design enhancement. When developing a fast multilevel switching device, increasing information density in the same silicon area is a desirable feature. In this design and analysis, a unique memristor-based CMOS inverter is presented. A unique inverter with a nonvolatile output and good performance. This characteristic makes it useful for a substitute inverter as well as an SRAM memory cell that supports input negation for special uses. Memristor-based CMOS design is an emerging concept that targets efficient memory computing systems. Simulations were performed in cadence using a memristor model extracted to analyze and compare power consumption. The analyses of non-volatility, the voltage produced, and the read/write period were performed with cadence virtuoso 130 nm CMOS technology using a power supply voltage of 1.9 V while consuming 35.67 µW, and the delay is 9.235 ps. The comparison with a pure CMOS implementation is promising in terms of power, area and delay significant improvement. Further, the Monte Carlo simulation results using 2000 samples confirmed the total power and delay of the proposed design.