Memory-processor co-scheduling in fixed priority systems

Alessandra Melani,Giorgio Buttazzo,Alberto Marchetti-Spaccamela,Vincenzo Bonifaci,Marko Bertogna

doi:10.1145/2834848.2834854

Abstract

A major obstacle towards the adoption of multi-core platforms for real-time systems is given by the difficulties in characterizing the interference due to memory contention. The simple fact that multiple cores may simultaneously access shared memory and communication resources introduces a significant pessimism in the timing and schedulability analysis. To counter this problem, predictable execution models have been proposed splitting task executions into two consecutive phases: a memory phase in which the required instruction and data are pre-fetched to local memory (M-phase), and an execution phase in which the task is executed with no memory contention (C-phase). Decoupling memory and execution phases not only simplifies the timing analysis, but it also allows a more efficient (and predictable) pipelining of memory and execution phases through proper co-scheduling algorithms.In this paper, we take a further step towards the design of smart co-scheduling algorithms for sporadic real-time tasks complying with the M/C (memory-computation) model. We provide a theoretical framework that aims at tightly characterizing the schedulability improvement obtainable with the adopted M/C task model on a single-core systems. We identify a tight critical instant for M/C tasks scheduled with fixed priority, providing an exact response-time analysis with pseudo-polynomial complexity. We show in our experiments that a significant schedulability improvement may be obtained with respect to classic execution models, placing an important building block towards the design of more efficient partitioned multi-core systems.

Highlights

Classic real-time scheduling techniques are being challenged by the advent of many-core platforms integrating a large number of computing units on a single chip
To distinguish this model from the generality of the task models adopted within the Predictable Execution Model (PREM) framework, we will denote it as M/C task model
To provide an experimental characterization of the performance improvement that may be obtained adopting the M/C task model, we conducted a set of experiments applying the schedulability test proposed in Section 4 to randomly generated M/C workloads scheduled with fixed-priority on a single-core/single-memory setting

Summary

Introduction

Classic real-time scheduling techniques are being challenged by the advent of many-core platforms integrating a large number of computing units on a single chip. As the core-count increases, the number of computing units becomes comparable to the number of tasks in the system, making the scheduling of the processing bandwidth less of a problem Another problem is jeopardizing the predictable exploitation of the huge computing power o↵ered by these systems: the relatively slow access to memory and communication resources. A major e↵ort in this sense is represented by the PREM scheduling framework introduced in [32] Within this framework, tasks are split into di↵erent phases: a memory phase in which the task pre-fetches the required instruction and data from memory and/or I/O devices (M-phase), and an execution phase in which the task executes without needing to access shared memory and communication devices (C-phase). To distinguish this model from the generality of the task models adopted within the PREM framework, we will denote it as M/C task model

Objectives

Results

Conclusion