Abstract
In the era of multi-core processors, the challenge of designing a high efficient memory system is more severe than before. This paper focuses on the memory hierarchy design and implementation on a multiprocessor system. With the distributed shared memory (DSM) model, some techniques have been presented to improve the performance of traditional memory hierarchy and simplify the complexity of cache coherence logic. Moreover, the proposed memory system is in favor of power-saving by reducing the number of times to access the lower-level memory devices. The structure of the memory system has been implemented with a 0.18μm CMOS process and some experimental results are presented.
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