Memory Persistency: Semantics for Byte-Addressable Nonvolatile Memory Technologies

Abstract

Emerging nonvolatile memory technologies (NVRAM) promise the performance of DRAM with the persistence of disk. However, constraining the NVRAM write order, necessary to ensure recovery correctness, limits the NVRAM write concurrency and degrades throughput. New memory interfaces are required to efficiently describe write constraints and allow high-performance and high-concurrency data structures. The authors introduce memory persistency, a new approach to designing persistent memory interfaces that builds on the familiar framework of memory consistency to provide an interface for constraining the order in which persistent writes can occur with respect to failure. Similar to memory consistency, memory persistency models may be relaxed to improve performance. The authors describe the design space of memory persistency, introduce several memory persistency models, and evaluate their ability to expose NVRAM write concurrency. Their results show that relaxed persistency models can accelerate system throughput 30 times by reducing NVRAM write constraints.