Memory-Efficient LFSR Encoding and Weightage Driven Bit Transition for Improved Fault Coverage

Abstract

Linear Feedback Shift Registers (LFSRs) have been employed as test pattern generators in BIST for decades; however, an emerging problem with design constraints leads to a lot of improvements in this field. This paper presents a memory-efficient encoding-based method to generate test patterns for a given primitive polynomial LFSR TPG. Here, test patterns generated from LFSR are divided into groups and follow encoding to transform into multiple test patterns. These newly generated encoded test patterns are further divided into transitional and non-transitional blocks which control the bit transitions over encoded values. This weighted driven bit transition also prevents certain bit transitions that reduce the dynamic power as well during the testing process. This TPG technique can be used for generating both pseudo-random test sequence and deterministic pattern generation by allowing fine control over bit transition and appropriate encoder design with the least hardware complexity overhead. The proposed technique has experimented over ISCAS ‘85 and some sequential part of ISCAS ‘89 benchmark circuits to validate the superiority in terms of memory efficiency compared to some well-known LFSR reseeding techniques and the hardware complexity reduction during BIST implementation. The proposed encoded test pattern also achieves a minimum of 14% test data volume and toggle control scheme in power reduction.