Memory‐efficient architecture of circle Hough transform and its FPGA implementation for iris localisation

Abstract

This study presents a circle Hough transform (CHT) architecture that provides memory reduction between 74 and 93% without and with little degradation in the accuracy, respectively. For an image of P × Q pixels, the standard (direct) CHT requires a two-dimensional (2D) accumulator array of P × Q cells, but the proposed CHT uses a 2D accumulator array of (P/m) × (Q/n) cells for coarse circle detection and two 1D accumulator arrays of P × 1 and Q × 1 cells for fine detection, therein reducing the memory by a factor of m × n (approximately). The proposed CHT architecture was applied to iris localisation application and carried out its comprehensive evaluation. The average accuracy of the proposed CHT for iris localisation (inner plus outer iris-circle detection) is 98% with memory reduction of 87% compared with the direct CHT. The proposed CHT architecture was implemented on field programmable logic array targeting Xilinx Zynq device. The proposed CHT hardware takes processing time of 6.25 ms (average) for iris localisation in an image of 320 × 240 px2. The proposed work is compared with the previous work, which shows improved results. Finally, the effect of additive Gaussian noise on the CHT performance is investigated.