Memory Built-in Self Test in Multicore Chips with Mesh-Based Networks

Abstract

Using a packet-based built-in self test for RAM cores in mesh-based networks on chip (NoC) can reduce the BIST circuit's area cost. The proposed scheme reuses the NoC to transport test patterns to RAM such that routing doesn't limit the number of RAM cores tested. The scheme also achieves higher test parallelism than a typical parallel BIST by interleaving the read/write test operations.