Memory based architecture to implement simplified block LMS algorithm on FPGA

Abstract

Least Mean Square (LMS) algorithm is undoubtedly the most resorted to algorithm in diverse fields of engineering. Due to its simplicity it has been applied to solve numerous problems including side lobe reduction in matched filters, adaptive equalization, system identification, adaptive noise cancellation etc. In this paper we present a simple architecture for the implementation of a variant of Block LMS algorithm where the weight updation and error calculation are both calculated block wise. The algorithm performs considerably well with a slight trade off in the learning curve time and misadjustment, both of which can be adjusted by varying the step size depending on the requirement. The architecture can be further modified to perform the variants of LMS algorithm such as sign-sign, signerror and sign-data algorithms. The performance of the Simplified BLMS and LMS algorithms are compared in MATLAB simulations and the hardware outputs from the FPGA are verified with the simulations.