Abstract
It has been reported and verified in many design experiences that a judicious utilization of the page/burst access modes supported by DRAMs contributes a great reduction in not only the DRAM access latency but also DRAM's energy consumption. Recently, researchers showed that a careful arrangement of data variables in memory directly leads to a maximum utilization of the page/burst access modes for the variable accesses, but unfortunately, found that the problems are not tractable, consequently, resorting to simple (e.g., greedy) heuristic solutions to the problems. To improve the quality of existing solutions, we propose a new storage assignment technique, called zone/spl I.bar/alignment, for variables, which effectively exploits an efficient 0-1 ILP formulation and the temporal locality of variables' accesses in code.
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