Mechanistic Understanding of Polarization‐Type Potential‐Induced Degradation in Crystalline‐Silicon Photovoltaic Cell Modules

Abstract

Potential‐induced degradation (PID) has been identified as a central reliability issue of photovoltaic (PV) cell modules. Several types of PID depend on the cell structure. Among those types, polarization‐type PID, which is characterized by reductions in short‐circuit current density (JSC) and open‐circuit voltage (VOC), is the fastest PID mode. Additionally, polarization‐type PID occurs readily at room temperature or at markedly low magnitudes of electric potential difference. Therefore, polarization‐type PID is a severe difficulty affecting silicon PV modules. Recently, degradation behavior, preventive measures, and mechanism have been investigated. As described herein, mechanistic aspects of polarization‐type PID are specifically examined and details of a recently proposed model involving a charge accumulation process at K centers in SiNx dielectric layers: the K‐center model are discussed. The K‐center model consistently explains previously reported results of experimentation, which indicates the validity of this model. Discussions presented herein are expected to improve the mechanistic understanding of polarization‐type PID in the PV community and to stimulate further discussions and verifications of the model.