Abstract
Defects such as cracks and voids are generated in the layer by electrical discharge coating. An effective method for suppressing the defects is not established because the mechanism of the defect generation has not been clarified. In this study, we investigated the characteristics of the TiC layer and Si layer on S50C by electrical discharge coating, and compared the generation state of the defects in the layers. In addition, we investigated the generation process of the defects in the layers. As a result, it was found that cracks and voids were generated in the TiC layer, and voids were generated and cracks were not generated in the Si layer. The number of voids in the TiC layer was greater than that in the Si layer. Compared with the whole surface of the TiC layer, the concentration of Fe at the voids of the layer was high and that of Ti and C was low. Compared with the whole surface of the Si layer, the concentration of Fe at the voids of the layer was high and that of Si and C was low. It became clear that neither crack nor void was generated in the first single discharge craters on the workpiece in the TiC layer and Si layer. Several voids and cracks were generated in the TiC layer and a few voids were generated in the Si layer when two or more of the discharge craters were deposited by progress of the coating.
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