Mechanical Stress during Grinding and Non-top Chip Inspection Technology of Stacked POP Packages

Abstract

A new type of PoP device with 4 memory chips and a lead frame layer was chosen for studying in this paper. The internal structure topography was observed by X-ray inspection technology from the x and y axis direction of the stacked package device to evaluate the position, area, number, depth and lead interconnection type of each chip inside the package. In addition, the removal mechanism of the packaging material, the grinding force and stress distribution of the internal structure during the grinding process along the z-axis of the stacked package under different grinding conditions (grinding speed, grinding depth) were studied by the establishment of a grinding simulation model to accurately expose the location and morphology of layer-by-layer defects in the stacked packaged chip. Moreover, chip positioning and defect morphology of the memory device package with PoP structure were definitely verified by the combination of X-ray inspection technology and chemical mechanical grinding, which proved to be an effective analytical method for stacked PoP package non-top chips.