Abstract
This chapter studies an efficient and accurate full-chip thermo-mechanical stress and reliability analysis tool and design optimization methodology to alleviate mechanical reliability issues in 3D ICs [5]. First, we analyze the detailed thermo-mechanical stress induced by TSVs in conjunction with various associated structures such as a landing pad and a dielectric liner. Then, we explore and validate the linear superposition principle of stress tensors and demonstrate the accuracy of this method against detailed finite element analysis (FEA) simulations. Next, we apply this linear superposition method to full-chip stress simulation and a reliability metric named the von Mises yield criterion. Finally, we study a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs. Our numerical experimental results demonstrate the effectiveness of the proposed methodology.
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