Measuring the high performance of five-stage ring VCO with reverse body bias technique in 45 nm CMOS technology

Abstract

In the CMOS, nanoscale technology power dissipation is becoming important metric. In presented work low leakage voltage controlled, ring systems oscillator circuit is proposed for critical communication systems with high oscillation frequency. An ideal approach has been investigated with substrate biasing technique for reduction of power consumption. We have shown simulation using cadence spectre 45 nm standard CMOS technology at room temperature (27°C) with supply voltage (Vdd=0.7 V). The simulation results provide efficient low power VCO in term of leakage power min (2.23 pW) and active power (9.03 nW) and max oscillation frequency (20.2 GHz) with joint PMOS and NMOS reverse substrate bias in comparison to PMOS and NMOS reverse substrate bias technique.