Abstract
In designing digital VLSI circuits, it is important to determine before fabrication the maximum speed at which the circuits can operate. Simulators that use critical path calculation, e.g. crystal, usually give very conservative results because no node logic values are assumed. Therefore, it is more accurate to use circuit simulations to determine the delay time (and hence the speed) of digital circuits. In this situation, to reduce simulation time, the minimization of the test pattern size becomes the primary issue. In this paper a simple but highly effective method to determine the worst-case delay time of digital circuits with known structures is presented. The method is applied to arithmetic units, such as adders.
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