Measurements and Analysis of Substrate Noise Coupling in TSV-Based 3-D Integrated Circuits

Abstract

Silicon substrates can be strategically isolated or unified among tiers in a through-silicon-via (TSV)-based 3-D integrated circuit (IC) structure, for the suppression of intertier substrate noise coupling or the reduction of grounding impedance of silicon substrates as a whole, respectively. A two-tier 3-D IC demonstrator in a 130-nm CMOS technology was successfully tested and analyzed with respect to intra and intertier substrate noise coupling. Each tier in the stack includes digital noise source circuits (NSs) and substrate noise monitors, and embodies in-place measurements of substrate noise coupling. An equivalent circuit unifies power and substrate networks of the tiers and simulates the frequency-domain response of substrate noise coupling. Measurements and calculation with the equivalent circuit are consistent for frequency dependency of substrate noise coupling in a 3-D IC demonstrator. Intratier propagation is dominant, while intertier coupling is insignificant for low-frequency substrate noise components. Intertier coupling becomes comparable with and finally overwhelms intratier coupling as the frequency of substrate noise components increases. Substrate noise coupling in a multitier chip stack is strongly impacted by the parasitic capacitance of TSVs, while that coupling becomes predictable with the equivalent circuit of the entire stack.