Abstract
This paper presents a small-area monolithic pixel detector ASIC designed in 130 nm SiGe BiCMOS technology for the upgrade of the pre-shower detector of the FASER experiment at CERN. The purpose of this prototype is to study the integration of fast front-end electronics inside the sensitive area of the pixels and to identify the configuration that could satisfy at best the specifications of the experiment. Self-induced noise, instabilities and cross-talk were minimised to cope with the several challenges associated to the integration of pre-amplifiers and discriminators inside the pixels. The methodology used in the characterisation and the design choices will also be described. Two of the variants studied here will be implemented in the pre-production ASIC of the FASER experiment pre-shower for further tests.
Highlights
SiGe BiCMOS technology for the upgrade of the pre-shower detector of the FASER experiment at CERN
The pixel-detector prototype described in this work is characterized by a monolithic structure, the pixelated sensitive area is integrated in the same chip with the front-end electronics
The gain of the architecture is one of the highest among all because, despite the connection with the pre-amplifier input is longer than the other versions, the capacitance of the sensitive area is smaller since no triple-well is needed for the integration of the electronics
Summary
The pixel-detector prototype described in this work is characterized by a monolithic structure, the pixelated sensitive area is integrated in the same chip with the front-end electronics. The reason behind the choice of this shape is to have 120◦ instead of 90◦ angles at the edges of the pixel sensitive areas to reduce the electric field in these zones and the risk of an early breakdown in the pixel matrix [7, 15, 16] In this way, it is possible to bias the pixels with higher voltages potentially leading to better performance [17]. The output of pixels in the same row are multiplexed as in Figure 2 making each superpixel able to distinguish simultaneous events only in the vertical direction This architectural choice enables integrating a smaller number of TDC channels in the chip with a consequent reduction of the power consumption and inactive area within the superpixel, that in the case of this prototype chip is less than 9 % of the total superpixel surface. Successive full-simulation studies have shown that the optimal pixel size is hexagonal with 65 μm side (corresponding approximately to a pixel pitch of 100 μm), which has been adopted for the final ASIC
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