Measurement of semiconductor–insulator interface states by constant-capacitance deep-level transient spectroscopy

Abstract

Localized electronic states at the semiconductor–insulator interface adversely affect the operation of insulated-gate, field-effect devices. Characterization of interface states provides essential information for minimizing their effect through process optimization, for predicting device performance, and ultimately for microscopic identification of interface defects. This paper reviews the application of deep-level transient spectroscopy (DLTS) for characterizing interface states on metal–insulator–semiconductor capacitors, with emphasis on the constant-capacitance (CC) mode of measurement. The DLTS measurement yields both the energy distribution of interface states and their cross section for capturing free carriers. In addition, it has the versatility of being applicable to both interface and bulk defect characterization. The CC-DLTS technique offers the combined features of high sensitivity (<1×109 eV−1 cm−2), minimum signal distortion at high defect densities, high energy resolution, and the determination of dynamic properties. After a description of the measurement system and experimental procedures, the theoretical basis is developed for data reduction of majority-carrier-dominated transients for the following cases: (1) under saturating-pulse conditions and (2) with Fermi-level controlled trap occupancy. Under the first topic is included a summary of transient-current spectroscopy, and the second is illustrated with the energy-resolved DLTS technique. The presentation includes an analysis of the effect of surface generation on the DLTS measurement of interface states near the semiconductor midgap and an analysis of the limits of applicability of the transient-capaci tance mode for DLTS measurement of interface states. The techniques are illustrated with measurements of electronic defect levels at the Si–SiO2 interface.