Measurement of minimum-geometry MOS transistor capacitances

Abstract

A technique for measuring the gate and substrate capacitances of small-geometry MOS transistors is described. On-chip circuits are used to sense small capacitive currents across a reference capacitor. A low impedance signal is produced which can be interpreted using a commercial bus-addressable gain-phase instrument. The technique has been demonstrated using a 5-µm CMOS process, and experimental capacitance data from several devices (as small as 4 µm by 4 µm) are presented which show short- and narrow-channel capacitance effects. The technique is scalable, which will permit measurement of the minimum-geometry devices of future process technologies. In addition, the technique could be used to measure small-geometry inter-level capacitances. Finally, the limitations of the technique for device modeling and process evaluation are discussed.