Maximizing Performance of Microelectronic Thermoelectric Generators With Parasitic Thermal and Electrical Resistances

Abstract

Microelectronic thermoelectric (TE) generators ( $\mu $ TEGs), which are one potential solution to powering energy autonomous integrated circuits (ICs), are often performance limited because of parasitic electrical and thermal resistances in the $\mu $ TEG circuit. Parasitic performance loss can be particularly severe for $\mu $ TEGs using materials with relatively low TE figure-of-merit, such as silicon (Si). In such cases, careful attention must be paid to optimizing the entire $\mu $ TEG circuit, not just the TE material properties. Here, a quantitative model of $\mu $ TEG device performance is developed that includes all significant electrical and thermal parasitics commonly encountered in IC-compatible $\mu $ TEGs. The model gives a pair of coupled quadratic equations that can be analytically or numerically solved to determine power generation and efficiency. For given parasitic resistance and material property values, the model shows that the ratio (called here the packing fraction) of cross-sectional area occupied by TE elements to total cross-sectional area for heat flow per thermopile can be designed to maximize either power or efficiency, but not both simultaneously. For realistic material and device parameters, the optimum packing fraction is often only 1%–10%, lower than what is used in many $\mu $ TEG designs. The model accounts for the reported power generation of some example $\mu $ TEGs and provides guidance toward significant performance improvement.