MAVD: MPEG-2 audio video decode system on MDSP/sup TM/

Abstract

We have implemented a so/bvare on(v MPEG-2 Azidio Video Decode (MAVD) system on the Cradle MDSP architectlire arid we highlight the siritobilip of MDSP' architectrire to e.rpluit the data, algorithinic, and pipeline parallelization q/fered hv Video processing algoritlnw like the MPEG2 Video ./or real-time perJiirniance and efficient partitioning a/ Systeiir. Audio and Video Proces.sing 017 a single chip nniltiprocessor. Most e.xisting implementations extract either data or pipeline paralleli.sm along with Instmction Level Paralleli.sm (ILP) in their implementations. We disciics the design of MP@ML MPEG2 video decoding system and MPEG-2 Stereo Decode Svsten? on this shored memon, MDSP plulfbrm. We also highlight how tl7e processor scalahilit?, is exploited as part of the design on this architectirre. Althaiigh simiiltaneous audio-video decode on general-pirrpose processors provides ,/le.rihilip, they are not cost-effective. Most of the media prucesu0r.s exploit hardware acceleration in part or Jirll to alleviate the high-thro~ighprit demands pnt hv these algorithins; thewhy making tl7em inJlerih1e Jar other applications. With the fle.rihility ofired IJV the Cradle platform we cozrld design a video decoder that coiild scale Jiom fbsr MSP.s (Media Stream Proce.ssor that is a clrister ufone RISC arid hvo DSP processors) to eight MSPs and hrrild a single-chip solntian inchiding the 10 interfaces ,for, videa/aridio output. TI7e s,vstem l7a.s heen tested on Cradle's internal CRA20.03 evahiation hoard. Specific contributions inclrrde the mdtiple VLD algorithm and other heiiri.stic approaches like ea!-ly- termination IDCTJbrfast video decoding.