Mating Sensitivity Analysis and Statistical Verification for Efficient Yield Estimation

Abstract

Parametric yield is a significant threat to the reliability of nanoscale analog and mixed-signal circuits. A critical yet challenging problem of yield estimation is to account for multiple circuit performance. In this paper, we propose a novel nonparametric statistical verification methodology to efficiently estimate the parametric yield due to 65-nm technology for multiperformance constraints. Our proposed approach exploits the fact that circuit parameters variation has different impacts on the circuit performance. Hence, a global sensitivity analysis classifies the circuit parameters according to their influence on the desired circuit performances. Based on this classification, an efficient joint recurrence verification (JRV) algorithm, a procedure inspired from DNA analysis, is performed on the most “critical/influential” parameters. A global hypothesis testing procedure is then performed based on the computed JRV metrics. We demonstrate the effectiveness of our methodology on two benchmark circuits. The acquired results show the ability of our approach to handle multiple corners and multiple performances yield problems with up to $11 {\times }$ speedup compared to conventional techniques with an average error smaller than 3%.