Abstract
AbstractMulti-chip packages (MCP) are analyzed for high density CMOS packaging using package system simulation, a new systematic methodology for design and trade-off studies of electronic packages. Technology parameters for a representative CMOS chip, multi-chip package, and printed wiring board technology are defined. The effect of these technology parameters on the characteristics of the MCP are examined. The MCP's are optimized using simulated annealing. A large set of optimum MCP's has been found. Based on this set, MCP technology parameters are ranked and their implications on future high density MCP's discussed.
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