Materials limitations of amorphous-Si:H transistors

Abstract

Application of two-terminal (back-to-back diode) and three-terminal (FET) amorphous-Si:H devices to the matrix addressing of liquid-crystal displays (LCD) is discussed. a-Si:H back-to-back diodes appear to be suitable switching elements for displays of intermediate complexity. These devices are easy to fabricate and appear to have a high yield. A n analysis of matrix-addressed LCD's shows that FET's implemented in a low-mobility material, such as a-Si:H, are best suited for (medium) high-resolution capacitorless displays where competing technologies (CdSe, poly-Si) are likely to encounter difficulties in meeting the off requirements. Instabilities in a-Si:H-based devices were studied by fabricating inverted and noninverted FET's with a variety of gate dielectrics: SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> , both thermally grown and sputtered; Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> , both by GD and LPCVD; and evaporated SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> . Comparison of these devices, which are listed in decreasing order of stability, showed that a-Si:H FET's with thermal oxide were stable. In other devices, the decrease of the source-drain current I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</inf> with time was mainly caused by trapping at the semiconductor-dielectric interface. Feasibility of a-Si:H FET-addressed LCD's was studied by fabricating experimental 26 × 26 G-H LCD's by photolithographic methods on soda-lime glass substrates, using either GD Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> or sputtered SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> as a gate dielectric. FET's use a ring layout for the gate geometry to maximize the off resistance and a positive photoconductivity-feedback mechanism to maximize the on current and to minimize cumulative trapping. The Schottky contact inverted FET's ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L = 25</tex> µm; <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W = 3800</tex> µm) have a switching range > 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> . In dc conditions, at a source-drain voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_{SD} = 10</tex> V, the drain current I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</inf> is typical < 1 pA at a gate voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_{G} = 0</tex> and > 1 µA at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_{G} = 10</tex> V. The transistor characteristics are time dependent. The channel mobility, as derived from the linear (triode) regime is about µ <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</inf> = 0'02 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V . s at quasi-dc and increases with decreasing pulse length until it saturates at µ <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</inf> = 0.2 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V . s. I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</inf> decreases with time to about <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\frac{1}{2}</tex> to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\frac{1}{3}</tex> of its initial value in ambient light (operating devices) and to about <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\frac{1}{10}</tex> in the dark, mostly due to trapping in the gate dielectric. The time-dependent decrease in I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</inf> has been studied under dc conditions for the plasma-deposited SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> and Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> gate insulators and under pulse conditions for Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> . Auger depth-profile analysis shows that the properties of amorphous hydrogenated silicon FET's are not very sensitive to the incorporation of common residual gases (O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> , N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> ). Lifetime tests at room temperature and at 80°C for > 1 year have been carried out and the displays appear to be stable.