Abstract
Layered dielectric tunnel barriers are expected to greatly increase the program/erase speeds of nonvolatile floating gate memory devices and could allow both nanosecond program/erase times as well as archival data storage. We have correlated dielectric constants and band offsets with respect to silicon in order to help identify possible materials from which to construct these devices. A numerical model has been developed to assess potential layered tunnel barrier materials and structures suitable for integration into silicon electronics. With this model, we explore the relative dominance of Fowler–Nordheim tunneling and thermionic emission and we present simulated I–V curves for some candidate materials.
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