Material engineering of percolating silicon nanowire networks for reliable and efficient electronic devices

Abstract

Motivated to produce reliable and performant SiNW-based transistors, we present in this work how percolating networks composed of randomly oriented SiNWs, called nanonets, are a promising material if they are well engineered. We demonstrate that a proper material engineering of nanonets via alumina encapsulation allows to drastically enhance the electrical characteristics of back gate field effect transistors (FETs). Based on a simple, low temperature (≤400 °C) and up-scalable process of integration, the fabricated FETs exhibit a low off-current in the picoampere range while maintaining very good on-performance, up to the microampere and thus on-to-off ratio exceeding 105. As stated in this work, these nanonet-FETs present not only comparable electrical performances to reported single SiNW-based transistors with the same back-gated architecture but also good device-to-device reproducibility. This initial benchmarking clearly indicates that Si nanonet-based devices display essential features in terms of performances and fabrication process for sensing and flexible electronics.