Abstract
Two-dimensional (2D) material based FETs are being considered for future technology nodes and high performance logic applications. However, a comprehensive assessment of 2D material based FETs has been lacking for high performance logic applications considering appropriate system level figure-of-merits (FOMs) e.g. delay, and energy-delay product. In this paper, we present guidelines for 2D material based FETs to meet sub-10 nm high performance logic requirements focusing on material requirement, device design, energy-delay optimization for the first time. We show the need for 2D materials with smaller effective mass in the transport direction and anisotropicity to meet the performance requirement for future technology nodes. We present novel device designs with one such 2D material (monolayer black-phosphorus) to keep Moore’s alive for the HP logic in sub-5 nm gate length regime. With these device proposals we show that below 5 nm gate lengths 2D electrostatistics arising from gate stack design becomes more of a challenge than direct source-to-drain tunneling for 2D material-based FETs. Therefore, it is challenging to meet both delay and energy-delay requirement in sub-5 nm gate length regime without scaling both supply voltage (VDD) and effective-oxide-thickness (EOT) below 0.5 V and 0.5 nm respectively.
Highlights
Two-dimensional (2D) material based FETs are being considered for future technology nodes and high performance logic applications
We show the need for 2D materials with smaller effective mass in the transport direction and anisotropicity to meet the performance requirement for future technology nodes
We present novel device designs with one such 2D material to keep Moore’s alive for the HP logic in sub-5 nm gate length regime
Summary
Two-dimensional (2D) material based FETs are being considered for future technology nodes and high performance logic applications. We present novel device designs with one such 2D material (monolayer black-phosphorus) to keep Moore’s alive for the HP logic in sub-5 nm gate length regime With these device proposals we show that below 5 nm gate lengths 2D electrostatistics arising from gate stack design becomes more of a challenge than direct source-to-drain tunneling for 2D materialbased FETs. it is challenging to meet both delay and energy-delay requirement in sub-5 nm gate length regime without scaling both supply voltage (VDD) and effective-oxide-thickness (EOT) below 0.5 V and 0.5 nm respectively. These devices achieve 15% boost in ON current, 50% reduction in energy-delay product, and 0.5x area scaling[1, 2] To further continue this trend, alternative channel materials e.g. SiGe, Ge, III-V, and novel device architectures e.g. gate-all-around nanowire (NW) FETs are being explored for future technology nodes. For a given technology node, we show the selection of supply voltage (VDD) to achieve the required delay and an optimum energy-delay product (EDP)
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
