Material characterization and process modeling issues of high-k dielectrics for FET applications

Abstract

In this paper, characterization and modeling issues of high-k dielectrics are reviewed and investigated. At first, thermal and plasma enhanced atomic layer deposition (T-ALD and PE-ALD) process effects on high-k dielectric thin film characteristics is analyzed and neural network (NNet) process modeling methodology applied to high-k thin film processing is reviewed. Characteristic variations of high-k dielectric layers and process variation effects are then examined. Comparison of electrical characteristic variation and post-metallization annealing (PMA) effects on different high-k dielectric thin film grown by molecular beam epitaxy (MOMBE) process is also presented. Annealing effects in different ambient gas environments on device characteristics are also examined. Finally, the nanowire FET using the ZnO nanowire on HfO 2 dielectrics is presented for the next-generation FET applications.