Abstract

FinFET is a promising device concept towards the 32 nm CMOS technology node and beyond as it combines the benefits of multi-gated architecture, intrinsically having superior scaling behavior, with a highly manufacturable process. The present paper will deal with material aspects of the SOI FinFET integration. We investigate scalability, performance and variability of high aspect ratio trigate FinFETs fabricated with 193nm immersion lithography and conventional dry etch. The effect of gate stack conformality on device performance is studied. The use of ion implantation for extension and the selective epitaxial growth of Si to achieve larger contact area on the source/drain areas are discussed from a materials perspective.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.