Mask fabrication for VLSI using an electron beam exposure system

Abstract

This study describes the results of feature size distribution, pattern location accuracy, and level-to-level registration error on chrome master masks fabricated by an Ee−BES-40 electron beam exposure system. The system has the capability of high speed electron beam blanking at 40 MHz, the capacity for large size masks (with 6 in. mask cassettes), and an automatic cassette handling system. OEBR-100 (PGMA), as the electron beam negative resist, is used for 5 and 6 in. chrome masks. Both wet processing and dry plasma technology are used for chrome etching. Test patterns and 64 K DRAM TEG, as the practical pattern, are used in this study. More than 40 measurements are taken, uniformly distributed over 96 and 112 mm squares, and the feature size distribution is measured by a laser interferometer x–y measuring system. Pattern location accuracy and level-to-level registration error are obtained using the Ee−BES-40 quality assurance programs called market and plotmarket. market operates by scanning over the resist image of the test pattern, utilizing the normal fiducial mark location hardware. The following results are obtained: (1) Feature size distribution within the 6 in. mask: ±0.1 μm, (2) Level-to-level registration error: less than 0.1 μm. High quality masks with about 0.02 defects/cm2, and rapid throughput of ten masks in 6 h using the automatic ten cassette handling system are obtained.