Abstract
This paper describes a system for the automatic layout of VLSI circuits designed using Path Programmable Logic (PPL) methodology. A formal model has been developed which serves as a framework for the manipulation of PPL circuits. This model supports two basic operations: wire folding and wire splitting. User specified constraints guide the PPL layout process. External wires, those which reach outside of the circuit, may be routed to a particular edge, ordered, or placed adjacently. Heuristics are used to select folds. A heuristic has been developed which chooses those folds which place the fewest restrictions on the circuit. The MASHER system has been fully implemented and a number of real circuits have been laid out. Examples are presented comparing MASHER layouts with both hand layouts and other computer generated layouts.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
