Abstract
The design and implementation of a CMOS VLSI chip for data compression and decompression, using tree-based codes are described. The chip, called MARVLE, implements a memory-based architecture, for variable length encoding and decoding based on tree-based codes. The chip implements an architecture that is based on an efficient scheme for mapping the tree representing any binary code onto a memory device. A prototype 2- mu m chip has been designed and verified, and fabricated by MOSIS. The chip can yield a compression rate of 57 Mb/s and a decompression rate of 31 Mb/s with a clock rate of 50 MHz. The VLSI hardware can be used to implement the JPEG baseline compression scheme. >
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