Margin Dependence on Array Size for Asymmetric Resistive Memory Cell

Abstract

In this paper, an unselected cell negative bias scheme (UCNB) is used to improve the read-margin of a 1D1R array. An equivalent circuit of UCNB was established, and a theoretical analysis was then conducted. The role of R sense and its influence on read-margin as a function of array size are analyzed theoretically and simulated with SPICE tools. It shows that under certain R sense , read-margin rises first but decreases afterward with increasing array size. In UCNB scheme, lower read-margin can be achieved at large array size. Results demonstrate the large-scale integration ability of arrays based on asymmetric memory cells.