MAPS with pixel level sparsified readout: from standard CMOS to vertical integration

Abstract

In recent years, scaled CMOS technologies have led to an increased cell functional density and a better spatial resolution in monolithic active pixel sensors (MAPS) for vertexing applications. Advanced MAPS may also take advantage of CMOS process features such as the deep n-well (DNW) structure, which can be used as the charge collecting element of the detector. A new kind of DNW-MAPS, namely SDR1, which exploits the capabilities of vertical integration (3D) processes, is presented and discussed in this paper. 3D processes may offer significant advantages in terms of detection efficiency, pixel cell size and immunity from cross-talk, therefore complying with the severe constraints set by future HEP experiments. This work includes a description of the analog and digital circuits integrated in the SDR1 chip, together with circuit simulations. Device simulation results concerning detection efficiency will be also discussed.