Abstract
The Parallel Random Access Machine (PRAM) model describes an abstract register machine for analyzing the complexity and scalability of parallel algorithms. Unfortunately, it is not possible to implement this model directly in hardware but it is at least possible to emulate this abstract model on more realistic parallel machines. Moreover, the recent evolution of processor architectures towards a forthcoming many-core era seems to indicate that PRAM-derived hardware architectures may even become important in the near future. The Single-chip Cloud Computer (SCC) is a recent example for an experimental many-core processor. By means of this processor, researchers have the opportunity to investigate the requirements of tomorrow's software design and programming models. In this paper, we discuss if and how the PRAM model could be mapped onto the SCC by exploiting its many-core related hardware features.
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