Abstract
This paper presents a new approach to technology mapping of symmetric and partially-symmetric logic functions to Fine-Grain Cellular-Architecture FPGAs. The method is based on Ordered Binary Decision Diagrams (BDDs). Properties of symmetric functions are used to generate Reduced Ordered BDDs for symmetric and partially symmetric functions that can be easily mapped to the rectangular, locally connected arrays of CA-type FPGAs. The mapping method is presented for the existing FPGA architecture, and routing domain modification is suggested for improved mapping. Examples of FPGA layouts are given.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
