Mapping of image and network processing tasks on high-throughput CMOL FPGA circuits

Abstract

A simple two-terminal memristive device has excellent scaling properties. For example, devices with footprint below 10×10 nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> have been recently demonstrated and crossbar structures provide means of sustaining memristor density in large-scale circuits. While taking advantage of high density memristive devices is relatively straightforward in crossbar memory circuits, doing so efficiently in digital logic circuits still remains challenging. For example, only a small fraction (less than 1% on average) of memristive devices is actively utilized, i.e. turned to highly conductive state, in CMOL FPGA circuits which are configured to implement representative benchmark circuits. The main contribution of this paper is to demonstrate that such utilization can be much higher, more than 12%, in certain variety of CMOL FPGA circuits which are specifically designed for high throughput processing of streaming data. The high memristor device utilization is demonstrated by performing detailed mapping of network and image processing tasks and is mainly due to efficient use of high fan-in logic gates implementing exact and approximate pattern matching operations with streaming data. As a result of high utilization proposed circuits are estimated to have much higher computational throughput as compared to traditional approaches and represent a killer application which capitalizes efficiently on the density advantages of memristive devices.