Mapping instruction sequences onto EPOM-processor arrays: a framework for parallel data processing

Abstract

The paper introduces an optimized mapping methodology for mapping instruction sequences (ISs) onto EPOM-processor arrays. The new features of this mapping methodology result from a systematic specification and exploitation of both instruction and processor level parallelism: ultra-low granularity of ISs requires an allocation and scheduling of individual instructions onto the given processor array. Moreover, this mapping methodology is complete in the sense that it considers both array bus-bandwidths and processor resource constraints. The mapping methodology is based on two concepts: 1) instruction sequences (ISs) which represent a generalized form of directed cyclic graphs (DCGs) and allow efficient specification of algorithm parallelism, and graph nodes represent instructions from the instruction set of a target processor architecture (J.P. Theis, 1997); 2) the EPOM-processor architecture which represents an optimized target VLIW processor architecture for parallel implementation of ISs (J.P. Theis and L. Thiele, 1996) and especially suited for parallel image/multimedia processing (J.P. Theis and L. Thiele, 1995). Special attention is paid to the optimization, of the mapping process of ISs onto EPOM-processor arrays. Algorithm execution time minimization is used as optimization goal. The mapping methodology is partially based on integer linear programming and heuristic techniques. The solution time complexity is substantially reduced by developing a two-phase hierarchical model, decoupling processor array allocation from subsequent scheduling. The efficiency of this mapping methodology was validated through experimental results on ISs of well known algorithm routines.