Mapping hierarchical neural networks to VLSI hardware

Abstract

Electronic ANNs rely heavily on the use of two-dimensional silicon and PCB substrates. Use of these substrates results in hierarchical hardware that exhibits varying levels of connectivity. Numerous approaches have been developed for generating hierarchical neural networks, however, generating hierarchical networks is only part of the problem. Equally important is the task of mapping hierarchical networks onto the hierarchical hardware. It will be shown theoretically and experimentally that, at least within a restricted domain, hierarchical networks can be mapped to hierarchical hardware more efficiently than nonhierarchical networks. The experimental hypothesis will be carried out through simulations with a number of clustering algorithms that rely on graph partitioning information. The clustering algorithms will also serve as a general purpose hierarchical hardware mapping tool. Their performance will be evaluated with both hierarchical and nonhierarchical test cases that include a MAXNET (pick maximum of inputs) application and a speech recognition task.