Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology

Abstract

Existing compilation techniques for coarse-grained reconfigurable arrays are closely related to approaches from the DSP world. These approaches employ several loop transformations, like pipelining or temporal partitioning, but they are not able to exploit the full parallelism of a given algorithm and the computational potential of a typical 2-dimensional array. In this paper: we present an overview of constraints which have to be considered when mapping applications to coarse-grained reconfigurable arrays; we present our design methodology for mapping regular algorithms onto massively parallel arrays which is characterised by loop parallelisation in the polytope model; and, in a first case study, we adapt our design methodology for targeting reconfigurable arrays. The case study shows that the presented regular mapping methodology may lead to highly efficient implementations taking into account the constraints of the architecture.