Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs

Abstract

In this paper, we propose a technique for an exhaustive testing of all the delay faults in the logic architecture of symmetrical FPGAs, in a Manufacturing-Oriented Test (MOT) context. Previous techniques, concerning the test of delay faults in an FPGA, have mainly focused on delay faults on interconnexions. Our technique enables the detection of delay faults in the logic architecture and can be viewed as a complementary approach to the previous ones. The method uses the reconfiguration property of the FPGA to make easier the test of delay faults. The configuration scheme consists in chaining the logic cells or the Look-Up Tables (LUTs) in a specific way. The chain connects each LUT output to one input of the next LUT. We demonstrate that the test of all the delay faults can be done with only two configurations and a reduced test sequence.