Manufacturability-aware physical layout optimizations

Abstract

Nanometer VLSI design is greatly challenged by the growing interdependency between manufacturing and design. Existing approaches in design for manufacturability (DFM) are still mostly post design, rather than during design. To really bridge the gap between design and manufacturing, it is important to model and feed proper manufacturing metrics and cost function upstream, especially at the key physical layout optimization stages such as routing and placement to have major impacts. In this paper, the authors show several aspects of the true manufacturability-aware physical design from lithography-aware routing to redundant-via aware routing to CMP aware floor planning and placement, and show their promises.