Manufacturability of the X Architecture at the 90-nm technology node

Abstract

In this paper, we discuss the results from a test chip that demonstrate the manufacturability and integration-worthiness of the X Architecture at the 90-nm technology node. We discuss how a collaborative effort between the design and chip making communities used the current generation of mask, lithography, wafer processing, inspection and metrology equipment to create 45 degree wires in typical metal pitches for the upper layers on a 90-nm device in a production environment. Cadence Design Systems created the test structure design and chip validation tools for the project. Canon’s KrF ES3 and ArF AS2 scanners were used for the lithography. Applied Materials used its interconnect fabrication technologies to produce the multilayer copper, low-k interconnect on 300-mm wafers. The results were confirmed for critical dimension and defect levels using Applied Materials’ wafer inspection and metrology systems.