Managing annealing pattern effects in 45 nm low power CMOS technology

Abstract

Device variability observed at intra-die scale is becoming more and more critical in recent CMOS technologies. This paper presents a study of the across die temperature dispersion induced by the interactions between the annealing processes and non-homogeneous designs patterned at the wafer surface. These phenomena, traditionally called patterned effects, are responsible for significant intra-die device dispersion. A complete optical and thermal simulation methodology that provides the intra-field temperature mapping has been developed and validated by electrical measurement to study these dispersions. This method has been used to quantify the variability induced by both the spike and laser activation anneals implemented in low power 45 nm CMOS platform. It was demonstrated first that the temperature fluctuations induced by the spike process are caused by non-uniform pattern layouts at the die scale. In particular, standard CMP dummy structures used to tile empty areas were found to be inadequate to avoid spike induced pattern effects. In addition, this simulation package proved that laser induced pattern effects are linked to layout inhomogeneities at a shorter scale because of a reduced heat diffusion length during this process. The spatial temperature dispersion phenomena were improved, at first, by decreasing the spatial optical dispersion through the optimization of dummy shapes and tiling (at long and short scale) close to the sensitive devices. The use of an absorbent layer in combination with the laser anneal was also investigated to minimize the spatial optical dispersion effects. A significant effort was carried out as well to reduce the temperature sensitivity of the most critical devices. Working in parallel in these two ways enabled us to suppress the intra-field device variability caused by the annealing pattern effects.