Management method for LSI wafer fabrication facilities: Tsutomu Tsuyama, Toshimasa Harada, Jun Nakazato and Kouichi Kubouchi. Proc. a. Reliab. Maintainab. Symp., 183 (1989)

Abstract

An experimental set-up was implemented by which metal-oxide-semiconductor (MOS) capacitors are subjected to bipolar high voltage (up to 20 V) pulses similar to those used in programming electrically erasable programmable read-only memory (EEPROM) devices. Thin (9 nm) tunnel SiO2 oxides MOS capacitors were used. During stress, by means of capacitive coupling, the capacitors gate node was kept floating so its potential was equivalent to that of the isolated floating gate of a memory cell. The written and erased operations of memory cells which are based on Fowler–Nordheim (FN) tunneling injection mechanisms, were then reproduced on simple MOS capacitors. Via a high input impedance electronic circuit, the floating gate potential was monitoring. A model based on a simple equivalent electrical circuit was used to simulate the transient regime of the FN current and the resulting floating gate charge and potential during dynamic stressing. It was shown that the floating gate accumulated charge is proportional to the maximum control gate voltage but is independent of the control gate pulse rise time.