Macromodeling of Nonlinear Transistor-Level Receiver Circuits

Abstract

In this paper, a modeling methodology for macromodeling transistor-level receiver circuits has been presented. A few receiver modeling techniques have been proposed in the past, but these modeling techniques only address the loading effect of the receiver circuits, i.e., the input characteristics of the receivers. In this paper, a modeling methodology that addresses both the loading effect as well as the output characteristics of the receiver has been proposed. This modeling technique is simple, accurate, and has huge computational speed-up over transistor-level receiver circuits. To model the input characteristics of the receiver, spline function with finite time difference (SFWFTD) and recurrent neural network (RNN) modeling methods have been used. The output characteristics of the receiver are modeled using a combination of receiver static characteristics and a delay element that takes into account the timing delay of the receiver. The accuracy of the modeling approach has been tested on some test cases and results show good accuracy and substantial speed-up compare to transistor-level receiver circuits. The proposed modeling technique has been extended to multiple ports to estimate sensitive effects like simultaneous switching noise (SSN) when multiple receivers are switching.