Macro-models for high-level area and power estimation on FPGAs

Abstract

This paper presents the high-level equation based area and power macro-models for various RTL level operators on FPGAs. The area model is parameterised with the bit width of the device and the power model takes into account input switching activity and input spatial correlation as well as input bit width. These models are derived by actual synthesis of these RTL operators using back-end logic synthesis and place-and-route tools. Compared with the other approaches, our method generated a uniform macro-model for each operator with fewer coefficients and sometimes lower degrees. It is also easier to analyse the power sensitivity to different parameters.